Phase Locked Loop Design

Even Andrea is proud This is not something that takes two clocks and puts the "new" one out in a "safe" way (you have to wait till the active clock goes LO before you switch to the other one) This is a module that has settings for the two frequencies and does the update in a smart way so you never see a glitch or a very long period from waiting to be "safe". Blew me away that Google gave me this for free Copy // prompt : veriloga module outputs one of two clock frequencies based on select input `include "disciplines.vams" `include "constants.vams" // Module to generate one of two clock frequencies module dual_freq_clock ( clk_out, select ); output clk_out; input select; electrical clk_out, select; // Parameters for clock frequencies and transitions parameter real freq1 = 100M; // First frequency (100 MHz) parameter real freq2 = 50M; // Second frequency (50 MHz) parameter real t_rise = 100p; ...