How Often Does Gen AI (and not even chatGPT) Get It Right First Time and For FREE??? (Google) - veriloga clock selector
| Even Andrea is proud |
This is not something that takes two clocks and puts the "new" one out in a "safe" way (you have to wait till the active clock goes LO before you switch to the other one)
This is a module that has settings for the two frequencies and does the update in a smart way so you never see a glitch or a very long period from waiting to be "safe".
Blew me away that Google gave me this for free
// prompt : veriloga module outputs one of two clock frequencies based on select input
`include "disciplines.vams"
`include "constants.vams"
// Module to generate one of two clock frequencies
module dual_freq_clock (
clk_out,
select
);
output clk_out;
input select;
electrical clk_out, select;
// Parameters for clock frequencies and transitions
parameter real freq1 = 100M; // First frequency (100 MHz)
parameter real freq2 = 50M; // Second frequency (50 MHz)
parameter real t_rise = 100p; // Rise time
parameter real t_fall = 100p; // Fall time
parameter real vdd = 1.8; // Supply voltage
parameter real vss = 0.0; // Ground voltage
parameter real v_thresh = (vdd + vss) / 2; // Threshold for the select signal
// Internal variables
real period;
real toggle_time;
integer toggle;
analog begin
// The `if-else` statement checks the value of the `select` input
// at each time step.
if (V(select) > v_thresh) begin
// If select is high, use the first frequency.
period = 1 / freq1;
end else begin
// If select is low, use the second frequency.
period = 1 / freq2;
end
// The `cross` function is used to schedule events based on time.
@(initial_step) begin
toggle = 0;
toggle_time = 0;
end
// Schedule the next toggle event.
@(timer(toggle_time)) begin
toggle = 1 - toggle; // Toggle the state (0 -> 1 or 1 -> 0)
toggle_time = $abstime + (period / 2); // Schedule the next toggle for half a period later
end
// Drive the output voltage based on the `toggle` variable.
V(clk_out) <+ transition(toggle * (vdd - vss) + vss, 0, t_rise, t_fall);
end
endmodule
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