Phase Locked Loop Design

Even Andrea is proud This is not something that takes two clocks and puts the "new" one out in a "safe" way (you have to wait till the active clock goes LO before you switch to the other one) This is a module that has settings for the two frequencies and does the update in a smart way so you never see a glitch or a very long period from waiting to be "safe". Blew me away that Google gave me this for free Copy // prompt : veriloga module outputs one of two clock frequencies based on select input `include "disciplines.vams" `include "constants.vams" // Module to generate one of two clock frequencies module dual_freq_clock ( clk_out, select ); output clk_out; input select; electrical clk_out, select; // Parameters for clock frequencies and transitions parameter real freq1 = 100M; // First frequency (100 MHz) parameter real freq2 = 50M; // Second frequency (50 MHz) parameter real t_rise = 100p; ...

Pros of using a very low CP current Lower reference spur amplitude The reference spurs are proportional to CP current and mismatch. Smaller current → smaller current pulses → reduced spur levels (at least ideally). Lower loop filter capacitor size For a given loop bandwidth, reducing CP current allows you to shrink the loop filter capacitance. This can save area in an integrated design if capacitor size is constrained. Lower power in the charge pump itself CP devices operate at smaller current, reducing static and dynamic power. Cons of using a very low CP current Increased sensitivity to current mismatch Absolute up/down mismatch errors don’t scale down linearly. As CP current is reduced, percentage mismatch and leakage matter more, which can cause static phase offset and reference spurs. Loop bandwidth shrinks Loop bandwidth ≈ (ICP × KVCO) / (N × C × Vctrl_swing). Smaller ICP → narrower bandwidth, unless you compensate with much smaller loop...

Q: I see Vc having a triangular profile with average value of f_out being correct. Does this ring a bell? Yep — that’s the classic PFD/charge-pump limit cycle (a.k.a. reference-spur triangle ripple). Why it happens Near lock, the UP/DN pulses should shrink toward zero. But any of the following makes there be a non-zero minimum pulse width or a net current imbalance , so the loop can’t settle to truly zero phase error. Instead it oscillates each reference cycle: Dead-zone / minimum pulse width in the PFD reset path (finite reset delay, flop delay, gates). Charge-pump non-overlap & edge slews (finite rise/fall, current source switching delay). UP/DN current mismatch or output-resistance mismatch → static phase offset that the loop “hunts” around. Anti-backlash pulses (if you inject a fixed pulse to avoid dead-zone, you also inject a fixed area each ref cycle). Too light loop filter (small Ceff) so the pump pulses create visible ripple. ...

“The key to science is not the answers, it’s the questions we ask.” - RPF Great question — this is a subtle but very important point in sampled-data feedback systems like digital PLLs. Background In a continuous-time loop, you can safely push the unity-gain bandwidth (UGBW) to a reasonable fraction of the loop's “available bandwidth” without worrying about aliasing or sampling. But in a sampled-data loop (like one with a PFD + divider running at reference frequency f REF ), the loop transfer function is effectively sampled at f REF . That means the Nyquist frequency of the sampled loop is only: f N = f REF / 2 The phase of the open-loop transfer function has to be evaluated not in continuous-time only, but also under the constraint that the digital updates occur every T REF = 1 / f REF . Quantitative Effect on Phase Margin The main penalty comes from extra delay equivalent to half a sampling period. This delay manifests as extra phase lag in the open-loop ...

For a ring oscillator, the more cap you can get on each stage, the better. For a ring oscillator, the more the VGST of the gain devices, the better. https://www2.eecs.berkeley.edu/Pubs/TechRpts/1998/ERL-98-5.pdf From a protege of Paul Gray The analysis shows that timing jitter is inversely proportional to the square root of the capacitance at the output of each inverter, and inversely proportional to the gatesource bias voltage above threshold of the source-coupled devices in the balanced state. Furthermore, these dependencies imply an inverse relationship between jitter and power consumption for an oscillator with a fixed output period. Phase noise and timing jitter are predicted to improve at a rate of 10 dB per decade increase in power consumption (and area). For a given output frequency and power consumption an oscillator with a minimum number of delay cell elements is desired to minimize timing jitter. These con clusions. as well as many practical considerations for ring-oscillato...

🔹 1. Exact vs. Approximate Models: Similar Math, Different Scope Both models reduce oscillator phase dynamics to a 1D equation driven by an input perturbation: Exact (Demir et al.) : Includes oscillator phase in its own evolution → nonlinear, more rigorous Approximate (Hajimiri & Lee) : Simpler integral form using ISF; easier to apply, but omits feedback For small perturbations and stationary noise , they yield identical phase noise predictions 🔹 2. Stationary Noise: Both Models Succeed Equally When noise input is stationary (e.g., thermal or 1/f noise) , the slow-phase behavior can be captured using averaging Averaging filters out high-frequency effects and isolates the core phase dynamics Both models reduce to the same stochastic differential equation, leading to the same phase noise growth (∝ √t) 🔹 3. Injection Locking: Only the Exact Model Captures It When driven by a non-stationary input (e.g., sine wave), only the exact model predicts phase and ...