Phase Locked Loop Design

Pros of using a very low CP current Lower reference spur amplitude The reference spurs are proportional to CP current and mismatch. Smaller current → smaller current pulses → reduced spur levels (at least ideally). Lower loop filter capacitor size For a given loop bandwidth, reducing CP current allows you to shrink the loop filter capacitance. This can save area in an integrated design if capacitor size is constrained. Lower power in the charge pump itself CP devices operate at smaller current, reducing static and dynamic power. Cons of using a very low CP current Increased sensitivity to current mismatch Absolute up/down mismatch errors don’t scale down linearly. As CP current is reduced, percentage mismatch and leakage matter more, which can cause static phase offset and reference spurs. Loop bandwidth shrinks Loop bandwidth ≈ (ICP × KVCO) / (N × C × Vctrl_swing). Smaller ICP → narrower bandwidth, unless you compensate with much smaller loop...

Q: I see Vc having a triangular profile with average value of f_out being correct. Does this ring a bell? Yep — that’s the classic PFD/charge-pump limit cycle (a.k.a. reference-spur triangle ripple). Why it happens Near lock, the UP/DN pulses should shrink toward zero. But any of the following makes there be a non-zero minimum pulse width or a net current imbalance , so the loop can’t settle to truly zero phase error. Instead it oscillates each reference cycle: Dead-zone / minimum pulse width in the PFD reset path (finite reset delay, flop delay, gates). Charge-pump non-overlap & edge slews (finite rise/fall, current source switching delay). UP/DN current mismatch or output-resistance mismatch → static phase offset that the loop “hunts” around. Anti-backlash pulses (if you inject a fixed pulse to avoid dead-zone, you also inject a fixed area each ref cycle). Too light loop filter (small Ceff) so the pump pulses create visible ripple. ...

“The key to science is not the answers, it’s the questions we ask.” - RPF Great question — this is a subtle but very important point in sampled-data feedback systems like digital PLLs. Background In a continuous-time loop, you can safely push the unity-gain bandwidth (UGBW) to a reasonable fraction of the loop's “available bandwidth” without worrying about aliasing or sampling. But in a sampled-data loop (like one with a PFD + divider running at reference frequency f REF ), the loop transfer function is effectively sampled at f REF . That means the Nyquist frequency of the sampled loop is only: f N = f REF / 2 The phase of the open-loop transfer function has to be evaluated not in continuous-time only, but also under the constraint that the digital updates occur every T REF = 1 / f REF . Quantitative Effect on Phase Margin The main penalty comes from extra delay equivalent to half a sampling period. This delay manifests as extra phase lag in the open-loop ...