The Todd Weigandt Thesis

For a ring oscillator, the more cap you can get on each stage, the better. For a ring oscillator, the more the VGST of the gain devices, the better.

https://www2.eecs.berkeley.edu/Pubs/TechRpts/1998/ERL-98-5.pdf


From a protege of Paul Gray

The analysis shows that timing jitter is inversely proportional to the square root of the capacitance at the output of each inverter, and inversely proportional to the gatesource bias voltage above threshold of the source-coupled devices in the balanced state. Furthermore, these dependencies imply an inverse relationship between jitter and power consumption for an oscillator with a fixed output period. Phase noise and timing jitter are predicted to improve at a rate of 10 dB per decade increase in power consumption (and area). For a given output frequency and power consumption an oscillator with a minimum number of delay cell elements is desired to minimize timing jitter. These con clusions. as well as many practical considerations for ring-oscillator VCO design arc described.

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