How High Can You Make UGF of Your PLL? (Relative to f_REF)

“The key to science is not the answers, it’s the questions we ask.” - RPF

Great question — this is a subtle but very important point in sampled-data feedback systems like digital PLLs.

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Background

In a continuous-time loop, you can safely push the unity-gain bandwidth (UGBW) to a reasonable fraction of the loop's “available bandwidth” without worrying about aliasing or sampling. But in a sampled-data loop (like one with a PFD + divider running at reference frequency fREF), the loop transfer function is effectively sampled at fREF.

That means the Nyquist frequency of the sampled loop is only:

f_N = f_REF / 2

The phase of the open-loop transfer function has to be evaluated not in continuous-time only, but also under the constraint that the digital updates occur every TREF = 1 / fREF.

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Quantitative Effect on Phase Margin

The main penalty comes from extra delay equivalent to half a sampling period. This delay manifests as extra phase lag in the open-loop response:

φ_sampling(ω) = − ω · T_REF / 2   (radians)

At the loop unity-gain frequency ωu = 2π fu, this lag is:

Δφ = − π · ( f_u / f_REF )

So the phase margin suffers linearly with the ratio of UGBW to reference frequency.

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Rule of Thumb

• If fu = fREF / 10, then
  Δφ ≈ −18°
• If fu = fREF / 5, then
  Δφ ≈ −36°
• If fu = fREF / 3, then
  Δφ ≈ −60°

Since most designers want ≥ 45° phase margin, this sets a practical ceiling:

f_u ≲ f_REF / 10   (safe zone)

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Intuition

The sampling essentially injects a transport delay into the loop dynamics. If the unity-gain bandwidth is too high compared to fREF, the effective delay consumes the phase margin and the loop risks instability (ringing, peaking, or even divergence).

This is why in digital PLL design guidelines, you’ll often see:

f_loop ≤ f_REF / 10

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✅ In short: The phase margin penalty is about −180° · ( fu / fREF ). That’s why designers usually limit the loop bandwidth to ~1/10 of the sampling rate (reference frequency).