How Low Can You Make Charge-Pump Current in a DPLL?



Pros of using a very low CP current

  1. Lower reference spur amplitude

    • The reference spurs are proportional to CP current and mismatch. Smaller current → smaller current pulses → reduced spur levels (at least ideally).

  2. Lower loop filter capacitor size

    • For a given loop bandwidth, reducing CP current allows you to shrink the loop filter capacitance. This can save area in an integrated design if capacitor size is constrained.

  3. Lower power in the charge pump itself

    • CP devices operate at smaller current, reducing static and dynamic power.

Cons of using a very low CP current

  1. Increased sensitivity to current mismatch

    • Absolute up/down mismatch errors don’t scale down linearly. As CP current is reduced, percentage mismatch and leakage matter more, which can cause static phase offset and reference spurs.

  2. Loop bandwidth shrinks

    • Loop bandwidth ≈ (ICP × KVCO) / (N × C × Vctrl_swing). Smaller ICP → narrower bandwidth, unless you compensate with much smaller loop-filter R/C.

    • Narrow loop = slower settling, poorer suppression of VCO noise close to the carrier.

  3. Susceptibility to leakage and charge sharing

    • With tiny currents, leakage on loop filter capacitors or switch charge injection can dominate, distorting the control voltage and increasing jitter.

  4. Worse PFD dead-zone behavior

    • At low current, small PFD pulses may not pump enough charge to overcome CP non-idealities (finite rise/fall, charge sharing), effectively increasing dead-zone and degrading in-band phase noise.

  5. Practical noise floor

    • Noise contributed by the CP switches themselves (flicker, thermal) doesn’t scale perfectly with current. At low current, you can actually worsen in-band noise because the loop bandwidth drops and CP noise is no longer negligible.

Rule of Thumb

  • Too high ICP: wide bandwidth, fast settling, but higher spurs and larger filter caps.

  • Too low ICP: clean spurs and small caps, but more mismatch errors, slow lock, and more leakage sensitivity.

Designers usually size ICP so that:

  • Loop bandwidth is ~1/10–1/20 of fREF,

  • Filter capacitor is within reasonable silicon area,

  • Current mismatch and leakage are negligible compared to the effective pulse charge.

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