Instability with a Triangular Vc (Control Voltage). How Would You Debug?

Q: I see Vc having a triangular profile with average value of f_out being correct. Does this ring a bell?

Yep — that’s the classic PFD/charge-pump limit cycle (a.k.a. reference-spur triangle ripple).

Why it happens

Near lock, the UP/DN pulses should shrink toward zero. But any of the following makes there be a non-zero minimum pulse width or a net current imbalance, so the loop can’t settle to truly zero phase error. Instead it oscillates each reference cycle:

  • Dead-zone / minimum pulse width in the PFD reset path (finite reset delay, flop delay, gates).
  • Charge-pump non-overlap & edge slews (finite rise/fall, current source switching delay).
  • UP/DN current mismatch or output-resistance mismatch → static phase offset that the loop “hunts” around.
  • Anti-backlash pulses (if you inject a fixed pulse to avoid dead-zone, you also inject a fixed area each ref cycle).
  • Too light loop filter (small Ceff) so the pump pulses create visible ripple.
  • Loop bandwidth too low vs fREF → the discrete-time “bang-bang-ish” behavior shows up as a limit cycle.
  • Leakage / bleed / charge sharing at the CP-LF node.

The result is a near-triangular VCTRL ripple at fREF (or a subharmonic) with the VCO averaging to the right frequency.

Quick checks to confirm

  • Scope the UP/DN pulses in lock. Do they stop shrinking below some width and alternate each cycle? That’s your limit cycle.
  • FFT of VCTRL. Big line at fREF (and its harmonics) → reference spur from CP pulses.
  • Swap in ideal PFD/CP (no delay, matched currents). If the triangle disappears, it’s the non-idealities above.

Back-of-envelope sizing

If UP/DN alternate with width tp, the peak-to-peak ripple is about

ΔVpp ≈ (ICP · tp) / Ceff

(First-order; a series R adds shaping.) So any non-zero tp or mismatch translates directly into a visible triangle on small Cₑff.

Knobs that usually fix it

  • Kill the dead-zone: speed up PFD reset; ensure UP/DN pulses overlap just enough so “true zero” phase gives zero net charge.
  • Match the CP currents (and output resistances) tightly; trim if possible.
  • Add a small bleed current (tens of µA relative to ICP): keeps the VCO varactor biased and linearizes around zero-error so pulses can truly cancel.
  • Increase the loop-filter C (or add a post-R shunt C) to attenuate pulse area → smaller ΔV.
  • Re-tune bandwidth: a common rule is fLBW ≲ fREF/10. If you’re much lower, the loop “samples” too coarsely and dithers.
  • Soften ICP if you’re overdriving a tiny C.
  • Mind anti-backlash: if you use it to remove dead-zone, keep the pulse area tiny or compensate with bleed/filtering.
  • Check fractional-N dither (if frac-N): ΣΔ settings can exacerbate apparent triangle/ripple if the loop is too light.

A minimal debug recipe

  1. Replace PFD/CP with ideal blocks → verify ripple vanishes.
  2. Bring back real PFD; speed up reset; ensure no dead-zone in sim.
  3. Bring back real CP; match UP/DN, add bleed, and increase Ceff.
  4. Retune loop to keep fLBW comfortably below fREF/10.
  5. Re-measure VCTRL FFT → reference spur should drop >20–40 dB, triangle becomes a small sawtooth or disappears.


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